1. Field of the Invention
Embodiments of the present invention generally relate to semiconductor manufacturing. More specifically, embodiments of the present invention relate to a method and a system for identifying and correcting locations in a routed layout of an integrated circuit (IC) chip that are susceptible to lithography errors.
2. Related Art
Advances in IC manufacturing technology have enabled minimum feature sizes on IC chips to continuously decrease. Meanwhile, manufacturability-aware physical design, which takes into account both yield and reliability during the physical-design process, is becoming increasingly important in bridging the gap between design and manufacturing for nanometer-scale fabrication processes. Many yield and reliability issues can be attributed to certain layout configurations, referred to as “process-hotspots” or “hotspots,” which are susceptible to process issues, such as stress and lithographic process fluctuations. It is therefore desirable to identify and remove these process-hotspot configurations and replace them with more yield-friendly configurations.
One of the main yield limiters is the increasing number of lithography “hotspots” that arise from the complexity of design layouts as technology nodes shrink to 65 nm and below. Although it is possible to deal with these lithography hotspots (“litho-hotspots” hereafter) during the resolution enhancement technology and optical proximity correction (RET/OPC) stage of the design cycle, it is becoming increasingly desirable to eliminate these litho-hotspots earlier in the design cycle (i.e., during or right after the physical design stage) because the RET/OPC stage has a heavy computational burden and little margin to effectively eliminate these lithography hotspots.
Conventionally, layout designers use manufacturer-provided design rules to represent litho-hotspots. A typical design rule checker can detect such litho-hotspots within the layout, which facilitates making corrections to the litho-hotspots to be compliant with the rules. However, this purely rule-based detection and correction approach has the drawback of introducing large number of false alarms. This drawback has become even more prominent as design rules become more numerous for sub-65 nm IC designs.
Another technique for detecting and correcting litho-hotspots involves manually fixing the hotspots by trial and error while using limited correction guidance information without taking into account the design rules. However, it is difficult to achieve a rapid and high-percentage correction convergence using this manual correction approach. Moreover, designers already have very limited time which makes such labor-intensive manual effort impractical.
Hence, what is needed is an automated and highly accurate litho-hotspot detection and correction technique which can be applied early in the IC design cycle.